PCI+Local+Bus+Specification+V3.0.pdf (3.39 MB)【资料名称】：PCI Local Bus Specification

【资料作者】：PCI-SIG

【资料日期】：February 3, 2004

【资料语言】：英文

【资料格式】：PDF

【资料目录和简介】：

Contents
PREFACE........................................................................................................................ 13
SPECIFICATION............................................................................................................... 13
INCORPORATION OF ENGINEERING CHANGE NOTICES (ECNS)....................................... 13
DOCUMENT CONVENTIONS ............................................................................................ 14
1. INTRODUCTION................................................................................................... 15
1.1. SPECIFICATION CONTENTS ................................................................................. 15
1.2. MOTIVATION...................................................................................................... 15
1.3. PCI LOCAL BUS APPLICATIONS ......................................................................... 16
1.4. PCI LOCAL BUS OVERVIEW............................................................................... 17
1.5. PCI LOCAL BUS FEATURES AND BENEFITS ........................................................ 18
1.6. ADMINISTRATION............................................................................................... 20
2. SIGNAL DEFINITION .......................................................................................... 21
2.1. SIGNAL TYPE DEFINITION .................................................................................. 22
2.2. PIN FUNCTIONAL GROUPS.................................................................................. 22
2.2.1. System Pins................................................................................................ 23
2.2.2. Address and Data Pins.............................................................................. 24
2.2.3. Interface Control Pins............................................................................... 25
2.2.4. Arbitration Pins (Bus Masters Only) ........................................................ 27
2.2.5. Error Reporting Pins................................................................................. 27
2.2.6. Interrupt Pins (Optional) .......................................................................... 28
2.2.7. Additional Signals ..................................................................................... 31
2.2.8. 64-Bit Bus Extension Pins (Optional) ....................................................... 33
2.2.9. JTAG/Boundary Scan Pins (Optional)...................................................... 34
2.2.10. System Management Bus Interface Pins (Optional) ................................. 35
2.3. SIDEBAND SIGNALS............................................................................................ 36
2.4. CENTRAL RESOURCE FUNCTIONS....................................................................... 36
3. BUS OPERATION.................................................................................................. 37
3.1. BUS COMMANDS ................................................................................................ 37
3.1.1. Command Definition ................................................................................. 37
3.1.2. Command Usage Rules ............................................................................. 39
3.2. PCI PROTOCOL FUNDAMENTALS ....................................................................... 42
3.2.1. Basic Transfer Control.............................................................................. 43
3.2.2. Addressing................................................................................................. 44
3.2.3. Byte Lane and Byte Enable Usage ............................................................ 56
3.2.4. Bus Driving and Turnaround .................................................................... 57
3.2.5. Transaction Ordering and Posting ........................................................... 58
3.2.6. Combining, Merging, and Collapsing....................................................... 62
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3.3. BUS TRANSACTIONS........................................................................................... 64
3.3.1. Read Transaction ...................................................................................... 65
3.3.2. Write Transaction...................................................................................... 66
3.3.3. Transaction Termination........................................................................... 67
3.4. ARBITRATION..................................................................................................... 87
3.4.1. Arbitration Signaling Protocol.................................................................. 89
3.4.2. Fast Back-to-Back Transactions ............................................................... 91
3.4.3. Arbitration Parking................................................................................... 94
3.5. LATENCY............................................................................................................ 95
3.5.1. Target Latency........................................................................................... 95
3.5.2. Master Data Latency................................................................................. 98
3.5.3. Memory Write Maximum Completion Time Limit..................................... 99
3.5.4. Arbitration Latency ................................................................................. 100
3.6. OTHER BUS OPERATIONS ................................................................................. 110
3.6.1. Device Selection ...................................................................................... 110
3.6.2. Special Cycle ........................................................................................... 111
3.6.3. IDSEL Stepping....................................................................................... 113
3.6.4. Interrupt Acknowledge ............................................................................ 114
3.7. ERROR FUNCTIONS........................................................................................... 115
3.7.1. Parity Generation.................................................................................... 115
3.7.2. Parity Checking....................................................................................... 116
3.7.3. Address Parity Errors ............................................................................. 116
3.7.4. Error Reporting....................................................................................... 117
3.7.5. Delayed Transactions and Data Parity Errors....................................... 120
3.7.6. Error Recovery........................................................................................ 121
3.8. 64-BIT BUS EXTENSION ................................................................................... 123
3.8.1. Determining Bus Width During System Initialization............................. 126
3.9. 64-BIT ADDRESSING......................................................................................... 127
3.10. SPECIAL DESIGN CONSIDERATIONS.............................................................. 130
4. ELECTRICAL SPECIFICATION...................................................................... 137
4.1. OVERVIEW ....................................................................................................... 137
4.1.1. Transition Road Map .............................................................................. 137
4.1.2. Dynamic vs. Static Drive Specification ................................................... 138
4.2. COMPONENT SPECIFICATION............................................................................ 139
4.2.1. 5V Signaling Environment ...................................................................... 140
4.2.2. 3.3V Signaling Environment ................................................................... 146
4.2.3. Timing Specification................................................................................ 150
4.2.4. Indeterminate Inputs and Metastability .................................................. 155
4.2.5. Vendor Provided Specification................................................................ 156
4.2.6. Pinout Recommendation ......................................................................... 157
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4.3. SYSTEM BOARD SPECIFICATION....................................................................... 158
4.3.1. Clock Skew .............................................................................................. 158
4.3.2. Reset ........................................................................................................ 158
4.3.3. Pull-ups ................................................................................................... 161
4.3.4. Power ...................................................................................................... 163
4.3.5. System Timing Budget ............................................................................. 164
4.3.6. Physical Requirements ............................................................................ 167
4.3.7. Connector Pin Assignments .................................................................... 168
4.4. ADD-IN CARD SPECIFICATION.......................................................................... 171
4.4.1. Add-in Card Pin Assignment................................................................... 171
4.4.2. Power Requirements ............................................................................... 176
4.4.3. Physical Requirements ............................................................................ 178
5. MECHANICAL SPECIFICATION.................................................................... 181
5.1. OVERVIEW ....................................................................................................... 181
5.2. ADD-IN CARD PHYSICAL DIMENSIONS AND TOLERANCES ............................... 182
5.3. CONNECTOR PHYSICAL DESCRIPTION .............................................................. 195
5.4. CONNECTOR PHYSICAL REQUIREMENTS .......................................................... 205
5.5. CONNECTOR PERFORMANCE SPECIFICATION.................................................... 206
5.6. SYSTEM BOARD IMPLEMENTATION .................................................................. 207
6. CONFIGURATION SPACE .................................................................................. 213
6.1. CONFIGURATION SPACE ORGANIZATION.......................................................... 213
6.2. CONFIGURATION SPACE FUNCTIONS ................................................................ 216
6.2.1. Device Identification ............................................................................... 216
6.2.2. Device Control ........................................................................................ 217
6.2.3. Device Status ........................................................................................... 219
6.2.4. Miscellaneous Registers.......................................................................... 221
6.2.5. Base Addresses........................................................................................ 224
6.3. PCI EXPANSION ROMS ................................................................................... 228
6.4. VITAL PRODUCT DATA..................................................................................... 229
6.5. DEVICE DRIVERS.............................................................................................. 229
6.6. SYSTEM RESET................................................................................................. 230
6.7. CAPABILITIES LIST ........................................................................................... 230
6.8. MESSAGE SIGNALED INTERRUPTS .................................................................... 231
6.8.1. MSI Capability Structure ........................................................................ 232
6.8.2. MSI-X Capability and Table Structures .................................................. 238
6.8.3. MSI and MSI-X Operation ...................................................................... 246
7. 66 MHZ PCI SPECIFICATION.......................................................................... 255
7.1. INTRODUCTION................................................................................................. 255
7.2. SCOPE............................................................................................................... 255
7.3. DEVICE IMPLEMENTATION CONSIDERATIONS .................................................. 255
7.3.1. Configuration Space................................................................................ 255
7.4. AGENT ARCHITECTURE .................................................................................... 256
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7.5. PROTOCOL........................................................................................................ 256
7.5.1. 66MHZ_ENABLE (M66EN) Pin Definition............................................ 256
7.5.2. Latency .................................................................................................... 257
7.6. ELECTRICAL SPECIFICATION ............................................................................ 257
7.6.1. Overview.................................................................................................. 257
7.6.2. Transition Roadmap to 66 MHz PCI ...................................................... 257
7.6.3. Signaling Environment............................................................................ 258
7.6.4. Timing Specification................................................................................ 259
7.6.5. Vendor Provided Specification................................................................ 265
7.6.6. Recommendations.................................................................................... 265
7.7. SYSTEM BOARD SPECIFICATION....................................................................... 266
7.7.1. Clock Uncertainty ................................................................................... 266
7.7.2. Reset ........................................................................................................ 267
7.7.3. Pullups..................................................................................................... 267
7.7.4. Power ...................................................................................................... 267
7.7.5. System Timing Budget ............................................................................. 268
7.7.6. Physical Requirements ............................................................................ 268
7.7.7. Connector Pin Assignments .................................................................... 269
7.8. ADD-IN CARD SPECIFICATIONS ........................................................................ 269
8. SYSTEM SUPPORT FOR SMBUS .................................................................... 271
8.1. SMBUS SYSTEM REQUIREMENTS..................................................................... 271
8.1.1. Power ...................................................................................................... 271
8.1.2. Physical and Logical SMBus................................................................... 271
8.1.3. Bus Connectivity...................................................................................... 272
8.1.4. Master and Slave Support ....................................................................... 273
8.1.5. Addressing and Configuration ................................................................ 273
8.1.6. Electrical ................................................................................................. 274
8.1.7. SMBus Behavior on PCI Reset................................................................ 274
8.2. ADD-IN CARD SMBUS REQUIREMENTS ........................................................... 275
8.2.1. Connection .............................................................................................. 275
8.2.2. Master and Slave Support ....................................................................... 275
8.2.3. Addressing and Configuration ................................................................ 275
8.2.4. Power ...................................................................................................... 275
8.2.5. Electrical ................................................................................................. 275
A. SPECIAL CYCLE MESSAGES.......................................................................... 277
A.1. MESSAGE ENCODINGS...................................................................................... 277
A.2. USE OF SPECIFIC ENCODINGS ........................................................................... 277
B. STATE MACHINES............................................................................................. 279
B.1. TARGET LOCK MACHINE................................................................................ 281
B.2. MASTER SEQUENCER MACHINE ....................................................................... 283
B.3. MASTER LOCK MACHINE ............................................................................... 284
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C. OPERATING RULES .......................................................................................... 289
C.1. WHEN SIGNALS ARE STABLE............................................................................ 289
C.2. MASTER SIGNALS............................................................................................. 290
C.3. TARGET SIGNALS ............................................................................................. 291
C.4. DATA PHASES .................................................................................................. 292
C.5. ARBITRATION................................................................................................... 292
C.6. LATENCY.......................................................................................................... 293
C.7. DEVICE SELECTION .......................................................................................... 293
C.8. PARITY............................................................................................................. 294
D. CLASS CODES..................................................................................................... 295
D.1. BASE CLASS 00H.............................................................................................. 296
D.2. BASE CLASS 01H.............................................................................................. 296
D.3. BASE CLASS 02H.............................................................................................. 297
D.4. BASE CLASS 03H.............................................................................................. 297
D.5. BASE CLASS 04H.............................................................................................. 298
D.6. BASE CLASS 05H.............................................................................................. 298
D.7. BASE CLASS 06H.............................................................................................. 299
D.8. BASE CLASS 07H.............................................................................................. 300
D.9. BASE CLASS 08H.............................................................................................. 301
D.10. BASE CLASS 09H.......................................................................................... 301
D.11. BASE CLASS 0AH......................................................................................... 302
D.12. BASE CLASS 0BH ......................................................................................... 302
D.13. BASE CLASS 0CH ......................................................................................... 303
D.14. BASE CLASS 0DH......................................................................................... 304
D.15. BASE CLASS 0EH ......................................................................................... 304
D.16. BASE CLASS 0FH.......................................................................................... 304
D.17. BASE CLASS 10H.......................................................................................... 305
D.18. BASE CLASS 11H.......................................................................................... 305
E. SYSTEM TRANSACTION ORDERING........................................................... 307
E.1. PRODUCER - CONSUMER ORDERING MODEL.................................................... 308
E.2. SUMMARY OF PCI ORDERING REQUIREMENTS ................................................ 310
E.3. ORDERING OF REQUESTS.................................................................................. 311
E.4. ORDERING OF DELAYED TRANSACTIONS ......................................................... 312
E.5. DELAYED TRANSACTIONS AND LOCK#........................................................... 317
E.6. ERROR CONDITIONS ......................................................................................... 318
F. EXCLUSIVE ACCESSES.................................................................................... 319
F.1. EXCLUSIVE ACCESSES ON PCI ......................................................................... 320
F.2. STARTING AN EXCLUSIVE ACCESS ................................................................... 321
F.3. CONTINUING AN EXCLUSIVE ACCESS............................................................... 323
F.4. ACCESSING A LOCKED AGENT ......................................................................... 324
F.5. COMPLETING AN EXCLUSIVE ACCESS .............................................................. 325
F.6. COMPLETE BUS LOCK ...................................................................................... 325
G. I/O SPACE ADDRESS DECODING FOR LEGACY DEVICES................ 327
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H. CAPABILITY IDS ............................................................................................ 329
I. VITAL PRODUCT DATA................................................................................... 331
I.1. VPD FORMAT .................................................................................................. 333
I.2. COMPATIBILITY................................................................................................ 334
I.3. VPD DEFINITIONS............................................................................................ 334
I.3.1. VPD Large and Small Resource Data Tags............................................ 334
I.3.2. VPD Example .......................................................................................... 337