The APZ 212 40 introduces a new system
principle. In place of the parallel synchronous
(lock-step) machine, we are introducing
a warm-standby/hot on-demand principle.
The CP has two independent sides, A and
B, that are loosely coupled via a high-speed
interconnect and a maintenance channel.
Each side contains two processors: one that
serves as an instruction processor unit (IPU),
and one that serves as a signal processor unit
(SPU), running as a two-way symmetrical
The APZ 212 40 is the first central processor of a new generation based on
industry-standard microprocessors. It introduces a new warm-standby/hot
on-demand system principle: the CP has two independent sides, each of
which contains two processors—one that serves as an instruction processing
unit and one that serves as a signal processing unit—which run
as a two-way symmetrical multiprocessing computer. The APZ virtual
machine handles ASA execution and is the middleware that guarantees
telecommunications-grade availability.
The authors describe the APZ 212 40 hardware and software, the
warm-standby concept for high availability, and differences and similarities
between this and previous APZ processors.
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