wcdma 规范
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HS-DPCCH
Figure 2A illustrates the frame. structure of the HS-DPCCH. The HS-DPCCH carries uplink feedback signalling related to downlink HS-DSCH transmission. The HS-DSCH-related feedback signalling consists of Hybrid-ARQ Acknowledgement (HARQ-ACK) and Channel-Quality Indication (CQI) and in case the UE is configured in MIMO mode of Precoding Control Indication (PCI) as well [3]. Each sub frame. of length 2 ms (3*2560 chips) consists of 3 slots, each of length 2560 chips. The HARQ-ACK is carried in the first slot of the HS-DPCCH sub-frame. The CQI, and in case the UE is configured in MIMO mode also the PCI, are carried in the second and third slot of a HS-DPCCH sub-frame. There is at most one HS-DPCCH on each radio link. The HS-DPCCH can only exist together with an uplink DPCCH. The timing of the HS-DPCCH relative to the uplink DPCCH is shown in section 7.7.MSCBSC | 移动通信网 rPZyqCI YWwk
MSCBSC | 移动通信网_-tM&\l!e
MSCBSC | 移动通信网 {M
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Figure 2A: Frame. structure for uplink HS-DPCCH
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The spreading factor of the HS-DPCCH is 256 i.e. there are 10 bits per uplink HS-DPCCH slot. The slot format for uplink HS-DPCCH is defined in Table 5A.MSCBSC | 移动通信网7Ne6vk&_+LQ#N
Table 5A: HS-DPCCH fields
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|
Slot Format #iMSCBSC | 移动通信网5p.}'T+W'm2[ |
Channel Bit Rate (kbps)MSCBSC | 移动通信网hH|;a#i&FA |
Channel Symbol Rate (ksps)MSCBSC | 移动通信网E?1VF D7xv |
SF j3^ C6B&|&\%P:p%r0k0 |
Bits/MSCBSC | 移动通信网)l7W;u#k!k X
Subframe 7e F1c]5{ ~ }
OY0 |
Bits/ l o/]g-@7Z9Q0
Slot HsDT+S?j'c0r0 |
Transmitted slots per Subframe :I
t^ NI:O;c0 |
|
0 E A#ZJt!r0FT h|4I0 |
15MSCBSC | 移动通信网 A(oOf@
uz7z'R
a |
15 V4Yg&R6y:z+?+t];l~0 |
256 o6y!C-X+r iWr0 |
30 6dRp3l+t*US \0 |
10MSCBSC | 移动通信网4F1E Q$cDs7C3g |
3 :l k DN*_;er:g"T4T0 |
(`3mF(il |L0
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